https://git.ruby-lang.org/ruby.git/commit/?id=9db2ca723c

From 9db2ca723cac60c2d65865a4851c13cac58ff6a3 Mon Sep 17 00:00:00 2001
From: Maxime Chevalier-Boisvert <maxime.chevalierboisvert@s...>
Date: Tue, 2 Aug 2022 15:36:27 -0400
Subject: Add 1 more allocatable reg on arm

---
 .cirrus.yml                   | 11 +++++++++++
 yjit/src/backend/arm64/mod.rs |  2 +-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/.cirrus.yml b/.cirrus.yml
index ef91abd3b2..839b4a6c17 100644
--- a/.cirrus.yml
+++ b/.cirrus.yml
@@ -153,4 +153,15 @@ yjit_task: https://github.com/ruby/ruby/blob/trunk/.cirrus.yml#L153
     bootstraptest/test_struct.rb \
     bootstraptest/test_yjit_new_backend.rb \
     bootstraptest/test_yjit_rust_port.rb
+
+  # These are the btests we can't run yet on arm:
+  #bootstraptest/test_block.rb (missing opt_send)
+  #bootstraptest/test_insns.rb (missing opt_send)
+  #bootstraptest/test_literal.rb (displacement bug)
+  #bootstraptest/test_syntax.rb (missing opt_send)
+  #bootstraptest/test_thread.rb (deadlock)
+  #bootstraptest/test_yjit.rb  (multiple bugs)
+  #bootstraptest/test_yjit_30k_ifelse.rb (missing opt_send)
+  #bootstraptest/test_yjit_30k_methods.rb (missing opt_send)
+
   # full_build_script: make -j
diff --git a/yjit/src/backend/arm64/mod.rs b/yjit/src/backend/arm64/mod.rs
index 99cf08c09c..e0e889c16c 100644
--- a/yjit/src/backend/arm64/mod.rs
+++ b/yjit/src/backend/arm64/mod.rs
@@ -66,7 +66,7 @@ impl Assembler https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/arm64/mod.rs#L66
     /// Note: we intentionally exclude C_RET_REG (X0) from this list
     /// because of the way it's used in gen_leave() and gen_leave_exit()
     pub fn get_alloc_regs() -> Vec<Reg> {
-        vec![X11_REG, X12_REG]
+        vec![X11_REG, X12_REG, X13_REG]
     }
 
     /// Get a list of all of the caller-saved registers
-- 
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