https://git.ruby-lang.org/ruby.git/commit/?id=40ac79ada8

From 40ac79ada89953f5ed9e36bdb5b3d0d3ae8d8f3e Mon Sep 17 00:00:00 2001
From: Maxime Chevalier-Boisvert <maxime.chevalierboisvert@s...>
Date: Wed, 15 Jun 2022 16:17:15 -0400
Subject: Add bitwise and to x86 backend

---
 yjit/src/backend/x86_64/mod.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/yjit/src/backend/x86_64/mod.rs b/yjit/src/backend/x86_64/mod.rs
index 7dcf41600d..e4f8745583 100644
--- a/yjit/src/backend/x86_64/mod.rs
+++ b/yjit/src/backend/x86_64/mod.rs
@@ -134,6 +134,10 @@ impl Assembler https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/x86_64/mod.rs#L134
                     add(cb, insn.opnds[0].into(), insn.opnds[1].into())
                 },
 
+                Op::And => {
+                    and(cb, insn.opnds[0].into(), insn.opnds[1].into())
+                },
+
                 Op::Store => mov(cb, insn.opnds[0].into(), insn.opnds[1].into()),
 
                 // This assumes only load instructions can contain references to GC'd Value operands
-- 
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