ruby-changes:73139
From: Kevin <ko1@a...>
Date: Tue, 30 Aug 2022 00:55:20 +0900 (JST)
Subject: [ruby-changes:73139] 1daa5942b8 (master): MOVK, MOVZ, BR (https://github.com/Shopify/ruby/pull/296)
https://git.ruby-lang.org/ruby.git/commit/?id=1daa5942b8 From 1daa5942b83ede3e504f9952a1f705b763e59893 Mon Sep 17 00:00:00 2001 From: Kevin Newton <kddnewton@g...> Date: Wed, 8 Jun 2022 15:19:53 -0400 Subject: MOVK, MOVZ, BR (https://github.com/Shopify/ruby/pull/296) * MOVK instruction * More tests for the A64 entrypoints * Finish testing entrypoints * MOVZ * BR instruction --- yjit/src/asm/arm64/inst/branch.rs | 85 ++++++++++ yjit/src/asm/arm64/inst/branches_and_system.rs | 62 ------- yjit/src/asm/arm64/inst/data_imm.rs | 172 ++++++++++++++++++++ .../asm/arm64/inst/data_processing_immediate.rs | 169 ------------------- .../src/asm/arm64/inst/data_processing_register.rs | 178 -------------------- yjit/src/asm/arm64/inst/data_reg.rs | 181 +++++++++++++++++++++ yjit/src/asm/arm64/inst/family.rs | 34 ---- yjit/src/asm/arm64/inst/load.rs | 100 ++++++++++++ yjit/src/asm/arm64/inst/loads_and_stores.rs | 99 ----------- yjit/src/asm/arm64/inst/mod.rs | 175 +++++++++++++++++--- yjit/src/asm/arm64/inst/mov.rs | 155 ++++++++++++++++++ yjit/src/asm/mod.rs | 12 ++ 12 files changed, 853 insertions(+), 569 deletions(-) create mode 100644 yjit/src/asm/arm64/inst/branch.rs delete mode 100644 yjit/src/asm/arm64/inst/branches_and_system.rs create mode 100644 yjit/src/asm/arm64/inst/data_imm.rs delete mode 100644 yjit/src/asm/arm64/inst/data_processing_immediate.rs delete mode 100644 yjit/src/asm/arm64/inst/data_processing_register.rs create mode 100644 yjit/src/asm/arm64/inst/data_reg.rs delete mode 100644 yjit/src/asm/arm64/inst/family.rs create mode 100644 yjit/src/asm/arm64/inst/load.rs delete mode 100644 yjit/src/asm/arm64/inst/loads_and_stores.rs create mode 100644 yjit/src/asm/arm64/inst/mov.rs diff --git a/yjit/src/asm/arm64/inst/branch.rs b/yjit/src/asm/arm64/inst/branch.rs new file mode 100644 index 0000000000..7f93f5e201 --- /dev/null +++ b/yjit/src/asm/arm64/inst/branch.rs @@ -0,0 +1,85 @@ https://github.com/ruby/ruby/blob/trunk/yjit/src/asm/arm64/inst/branch.rs#L1 +/// Which operation to perform. +enum Op { + /// Perform a BR instruction. + Br = 0b00, + + /// Perform a RET instruction. + Ret = 0b10 +} + +/// The struct that represents an A64 branch instruction that can be encoded. +/// +/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 | +/// | 1 1 0 1 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 | +/// | op... rn.............. rm.............. | +/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +/// +pub struct Branch { + /// The register holding the address to be branched to. + rn: u8, + + /// The operation to perform. + op: Op +} + +impl Branch { + /// BR + /// https://developer.arm.com/documentation/ddi0602/2022-03/Base-Instructions/BR--Branch-to-Register-?lang=en + pub fn br(rn: u8) -> Self { + Self { rn, op: Op::Br } + } + + /// RET + /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/RET--Return-from-subroutine-?lang=en + pub fn ret(rn: u8) -> Self { + Self { rn, op: Op::Ret } + } +} + +/// https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Branches--Exception-Generating-and-System-instructions?lang=en +const FAMILY: u32 = 0b101; + +impl From<Branch> for u32 { + /// Convert an instruction into a 32-bit value. + fn from(inst: Branch) -> Self { + 0 + | (0b11 << 30) + | (FAMILY << 26) + | (1 << 25) + | ((inst.op as u32) << 21) + | (0b11111 << 16) + | ((inst.rn as u32) << 5) + } +} + +impl From<Branch> for [u8; 4] { + /// Convert an instruction into a 4 byte array. + fn from(inst: Branch) -> [u8; 4] { + let result: u32 = inst.into(); + result.to_le_bytes() + } +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn test_br() { + let result: u32 = Branch::br(0).into(); + assert_eq!(0xd61f0000, result); + } + + #[test] + fn test_ret() { + let result: u32 = Branch::ret(30).into(); + assert_eq!(0xd65f03C0, result); + } + + #[test] + fn test_ret_rn() { + let result: u32 = Branch::ret(20).into(); + assert_eq!(0xd65f0280, result); + } +} diff --git a/yjit/src/asm/arm64/inst/branches_and_system.rs b/yjit/src/asm/arm64/inst/branches_and_system.rs deleted file mode 100644 index 77e99c112a..0000000000 --- a/yjit/src/asm/arm64/inst/branches_and_system.rs +++ /dev/null @@ -1,62 +0,0 @@ https://github.com/ruby/ruby/blob/trunk/yjit/src/asm/arm64/inst/branch.rs#L0 -use super::family::Family; - -/// The struct that represents an A64 branches and system instruction that can -/// be encoded. -/// -/// RET -/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 | -/// | 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 | -/// | rn.............. rm.............. | -/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ -/// -pub struct BranchesAndSystem { - /// The register holding the address to be branched to. - rn: u8 -} - -impl BranchesAndSystem { - /// RET - /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/RET--Return-from-subroutine-?lang=en - pub fn ret(rn: u8) -> Self { - Self { rn } - } -} - -impl From<BranchesAndSystem> for u32 { - /// Convert an instruction into a 32-bit value. - fn from(inst: BranchesAndSystem) -> Self { - 0 - | (0b11 << 30) - | ((Family::BranchesAndSystem as u32) << 25) - | (0b1001011111 << 16) - | ((inst.rn as u32) << 5) - } -} - -impl From<BranchesAndSystem> for [u8; 4] { - /// Convert an instruction into a 4 byte array. - fn from(inst: BranchesAndSystem) -> [u8; 4] { - let result: u32 = inst.into(); - result.to_le_bytes() - } -} - -#[cfg(test)] -mod tests { - use super::*; - - #[test] - fn test_ret() { - let inst = BranchesAndSystem::ret(30); - let result: u32 = inst.into(); - assert_eq!(0xd65f03C0, result); - } - - #[test] - fn test_ret_rn() { - let inst = BranchesAndSystem::ret(20); - let result: u32 = inst.into(); - assert_eq!(0xd65f0280, result); - } -} diff --git a/yjit/src/asm/arm64/inst/data_imm.rs b/yjit/src/asm/arm64/inst/data_imm.rs new file mode 100644 index 0000000000..0d0a6ff325 --- /dev/null +++ b/yjit/src/asm/arm64/inst/data_imm.rs @@ -0,0 +1,172 @@ https://github.com/ruby/ruby/blob/trunk/yjit/src/asm/arm64/inst/data_imm.rs#L1 +use super::sf::Sf; + +/// The operation being performed by this instruction. +enum Op { + Add = 0b0, + Sub = 0b1 +} + +// Whether or not to update the flags when this instruction is performed. +enum S { + LeaveFlags = 0b0, + UpdateFlags = 0b1 +} + +/// How much to shift the immediate by. +enum Shift { + LSL0 = 0b0, // no shift + LSL12 = 0b1 // logical shift left by 12 bits +} + +/// The struct that represents an A64 data processing -- immediate instruction +/// that can be encoded. +/// +/// Add/subtract (immediate) +/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 | +/// | 1 0 0 0 1 0 | +/// | sf op S sh imm12.................................... rn.............. rd.............. | +/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +/// +pub struct DataImm { + /// The register number of the destination register. + rd: u8, + + /// The register number of the first operand register. + rn: u8, + + /// The value of the immediate. + imm12: u16, + + /// How much to shift the immediate by. + shift: Shift, + + /// Whether or not to update the flags when this instruction is performed. + s: S, + + /// The opcode for this instruction. + op: Op, + + /// Whether or not this instruction is operating on 64-bit operands. + sf: Sf +} + +impl DataImm { + /// ADD (immediate) + /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADD--immediate---Add--immediate--?lang=en + pub fn add(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self { + Self { + rd, + rn, + imm12, + shift: Shift::LSL0, + s: S::LeaveFlags, + op: Op::Add, + sf: num_bits.into() + } + } + + /// ADDS (immediate, set flags) + /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADDS--immediate---Add--immediate---setting-flags-?lang=en + pub fn adds(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self { + Self { + rd, + rn, + imm12, + shift: Shift::LSL0, + s: S::UpdateFlags, + op: Op::Add, + sf: num_bits.into() + } + } + + /// SUB (immediate) + /// https://developer.arm.com/documentation/ddi0596/2021-1 (... truncated) -- ML: ruby-changes@q... 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