https://git.ruby-lang.org/ruby.git/commit/?id=a2aa289594

From a2aa289594352db98b893aae716cebae0556a20e Mon Sep 17 00:00:00 2001
From: Maxime Chevalier-Boisvert <maxime.chevalierboisvert@s...>
Date: Wed, 18 May 2022 11:36:55 -0400
Subject: Function to map from Opnd => X86Opnd

---
 yjit/src/asm/x86_64/mod.rs     |  4 +--
 yjit/src/backend/ir.rs         | 16 ++++++++----
 yjit/src/backend/x86_64/mod.rs | 59 +++++++++++++++++++++++++++++++-----------
 3 files changed, 57 insertions(+), 22 deletions(-)

diff --git a/yjit/src/asm/x86_64/mod.rs b/yjit/src/asm/x86_64/mod.rs
index 0a930ecf60..1f3dfd2e24 100644
--- a/yjit/src/asm/x86_64/mod.rs
+++ b/yjit/src/asm/x86_64/mod.rs
@@ -5,7 +5,7 @@ use crate::asm::*; https://github.com/ruby/ruby/blob/trunk/yjit/src/asm/x86_64/mod.rs#L5
 // Import the assembler tests module
 mod tests;
 
-#[derive(Clone, Copy, Debug)]
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
 pub struct X86Imm
 {
     // Size in bits
@@ -15,7 +15,7 @@ pub struct X86Imm https://github.com/ruby/ruby/blob/trunk/yjit/src/asm/x86_64/mod.rs#L15
     pub value: i64
 }
 
-#[derive(Clone, Copy, Debug)]
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
 pub struct X86UImm
 {
     // Size in bits
diff --git a/yjit/src/backend/ir.rs b/yjit/src/backend/ir.rs
index 9cff4aeac9..a561d4bb49 100644
--- a/yjit/src/backend/ir.rs
+++ b/yjit/src/backend/ir.rs
@@ -183,7 +183,7 @@ pub enum Op https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/ir.rs#L183
 pub struct Mem
 {
     // Base register
-    pub(super) base: Reg,
+    pub(super) base_reg: Reg,
 
     // Offset relative to the base pointer
     pub(super) disp: i32,
@@ -198,8 +198,11 @@ pub enum Opnd https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/ir.rs#L198
 {
     None,               // For insns with no output
 
-    Stack(u16),         // Value on the temp stack (idx)
-    Local(u16),         // Local variable (idx, do we need depth too?)
+    // NOTE: for now Context directly returns memory operands,
+    // but eventually we'd like to have Stack and Local operand types
+    //Stack(u16),         // Value on the temp stack (idx)
+    //Local(u16),         // Local variable (idx, do we need depth too?)
+
     Value(VALUE),       // Immediate Ruby value, may be GC'd, movable
     InsnOut(usize),     // Output of a preceding instruction in this block
 
@@ -219,7 +222,7 @@ impl Opnd https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/ir.rs#L222
                 assert!(base_reg.num_bits == 64);
                 Opnd::Mem(Mem {
                     num_bits: num_bits,
-                    base: base_reg,
+                    base_reg: base_reg,
                     disp: disp,
                 })
             },
@@ -228,6 +231,9 @@ impl Opnd https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/ir.rs#L231
     }
 }
 
+/// NOTE: this is useful during the port but can probably be removed once
+/// Context returns ir::Opnd instead of X86Opnd
+///
 /// Method to convert from an X86Opnd to an IR Opnd
 impl From<X86Opnd> for Opnd {
     fn from(opnd: X86Opnd) -> Self {
@@ -246,7 +252,7 @@ impl From<X86Opnd> for Opnd { https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/ir.rs#L252
                 let base_reg = Reg { num_bits: 64, reg_no: base_reg_no, reg_type: RegType::GP };
 
                 Opnd::Mem(Mem {
-                    base: base_reg,
+                    base_reg: base_reg,
                     disp,
                     num_bits
                 })
diff --git a/yjit/src/backend/x86_64/mod.rs b/yjit/src/backend/x86_64/mod.rs
index 257373e86f..67e220fd8b 100644
--- a/yjit/src/backend/x86_64/mod.rs
+++ b/yjit/src/backend/x86_64/mod.rs
@@ -14,6 +14,31 @@ pub const CFP: Opnd = Opnd::Reg(R13_REG); https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/x86_64/mod.rs#L14
 pub const EC: Opnd = Opnd::Reg(R12_REG);
 pub const SP: Opnd = Opnd::Reg(RBX_REG);
 
+/// Map Opnd to X86Opnd
+impl From<Opnd> for X86Opnd {
+    fn from(opnd: Opnd) -> Self {
+        match opnd {
+            //Value(VALUE),       // Immediate Ruby value, may be GC'd, movable
+            //InsnOut(usize),     // Output of a preceding instruction in this block
+
+            Opnd::None => X86Opnd::None,
+
+            Opnd::UImm(val) => uimm_opnd(val),
+            Opnd::Imm(val) => imm_opnd(val),
+
+            // General-purpose register
+            Opnd::Reg(reg) => X86Opnd::Reg(reg),
+
+            // Memory operand with displacement
+            Opnd::Mem(Mem{ num_bits, base_reg, disp }) => {
+                mem_opnd(num_bits, X86Opnd::Reg(base_reg), disp)
+            }
+
+            _ => panic!("unsupported x86 operand type")
+        }
+    }
+}
+
 impl Assembler
 {
     // Get the list of registers from which we can allocate on this platform
@@ -28,28 +53,32 @@ impl Assembler https://github.com/ruby/ruby/blob/trunk/yjit/src/backend/x86_64/mod.rs#L53
     // Emit platform-specific machine code
     pub fn target_emit(&self, cb: &mut CodeBlock)
     {
-
-
-
+        // For each instruction
         for insn in &self.insns {
-
-
-            // For each instruction, either handle it here or allow the map_insn
-            // callback to handle it.
             match insn.op {
-                Op::Comment => {
-                },
-                Op::Label => {
-                },
-                _ => {
-                }
-            };
+                Op::Comment => {},
+                Op::Label => {},
 
+                Op::Add => {
 
-        }
+                    //add(cb, )
 
 
 
+                },
 
+                /*
+                Load
+                Store,
+                Mov,
+                Test,
+                Cmp,
+                Jnz,
+                Jbe,
+                */
+
+                _ => panic!("unsupported instruction passed to x86 backend")
+            };
+        }
     }
 }
-- 
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