https://git.ruby-lang.org/ruby.git/commit/?id=96e5f9def0

From 96e5f9def0121a7ee4f1557b25dade7bdb558df8 Mon Sep 17 00:00:00 2001
From: Maxime Chevalier-Boisvert <maxime.chevalierboisvert@s...>
Date: Thu, 12 May 2022 13:55:49 -0400
Subject: Add macro to define ops

---
 yjit/src/ir.rs | 48 +++++++++++++++++++++++++++++-------------------
 1 file changed, 29 insertions(+), 19 deletions(-)

diff --git a/yjit/src/ir.rs b/yjit/src/ir.rs
index 8c35f7f615..d3cc76d2d1 100644
--- a/yjit/src/ir.rs
+++ b/yjit/src/ir.rs
@@ -254,12 +254,6 @@ pub enum Opnd https://github.com/ruby/ruby/blob/trunk/yjit/src/ir.rs#L254
     Reg(Reg),           // Machine register (num_bits, idx)
 }
 
-// Special register constants
-pub const EC    : Opnd = Opnd::Reg(Reg { reg_no: 0, num_bits: 64, special: true });
-pub const CFP   : Opnd = Opnd::Reg(Reg { reg_no: 1, num_bits: 64, special: true });
-pub const SP    : Opnd = Opnd::Reg(Reg { reg_no: 2, num_bits: 64, special: true });
-pub const SELF  : Opnd = Opnd::Reg(Reg { reg_no: 3, num_bits: 64, special: true });
-
 impl Opnd
 {
     // Convenience constructor for memory operands
@@ -278,6 +272,12 @@ impl Opnd https://github.com/ruby/ruby/blob/trunk/yjit/src/ir.rs#L272
     }
 }
 
+// Special register constants
+pub const EC    : Opnd = Opnd::Reg(Reg { reg_no: 0, num_bits: 64, special: true });
+pub const CFP   : Opnd = Opnd::Reg(Reg { reg_no: 1, num_bits: 64, special: true });
+pub const SP    : Opnd = Opnd::Reg(Reg { reg_no: 2, num_bits: 64, special: true });
+pub const SELF  : Opnd = Opnd::Reg(Reg { reg_no: 3, num_bits: 64, special: true });
+
 /// Method to convert from an X86Opnd to an IR Opnd
 impl From<X86Opnd> for Opnd {
     fn from(opnd: X86Opnd) -> Self {
@@ -335,6 +335,7 @@ pub struct Insn https://github.com/ruby/ruby/blob/trunk/yjit/src/ir.rs#L335
     // List of input operands/values
     opnds: Vec<Opnd>,
 
+    // Kevin asks: do we really need multiple branch targets?
     // List of branch targets (branch instructions only)
     targets: Vec<Target>,
 
@@ -397,10 +398,12 @@ impl Assembler https://github.com/ruby/ruby/blob/trunk/yjit/src/ir.rs#L398
         self.push_insn(Op::Add, vec![ Opnd::String(text.to_owned()) ], vec![]);
     }
 
+    /*
     fn add(&mut self, opnd0: Opnd, opnd1: Opnd) -> Opnd
     {
         self.push_insn(Op::Add, vec![opnd0, opnd1], vec![])
     }
+    */
 
     // Low-level, no output operand
     fn test(&mut self, opnd0: Opnd, opnd1: Opnd)
@@ -408,23 +411,34 @@ impl Assembler https://github.com/ruby/ruby/blob/trunk/yjit/src/ir.rs#L411
         self.push_insn(Op::Add, vec![opnd0, opnd1], vec![]);
     }
 
-    // Jump if not zero
-    fn jnz(&mut self, target: Target)
-    {
-        self.push_insn(Op::Jnz, vec![], vec![target]);
-    }
-
     // Low-level, no output operand
     fn mov(&mut self, opnd0: Opnd, opnd1: Opnd)
     {
         self.push_insn(Op::Add, vec![opnd0, opnd1], vec![]);
     }
-}
-
-
 
+    // Jump if not zero
+    fn jnz(&mut self, target: Target)
+    {
+        self.push_insn(Op::Jnz, vec![], vec![target]);
+    }
+}
 
+macro_rules! def_push_insn_2_opnd {
+    ($op_name:ident, $opcode:expr) => {
+        impl Assembler
+        {
+            fn $op_name(&mut self, opnd0: Opnd, opnd1: Opnd) -> Opnd
+            {
+                self.push_insn($opcode, vec![opnd0, opnd1], vec![])
+            }
+        }
+    };
+}
 
+def_push_insn_2_opnd!(add, Op::Add);
+def_push_insn_2_opnd!(sub, Op::Sub);
+def_push_insn_2_opnd!(and, Op::And);
 
 // NOTE: these methods are temporary and will likely move
 // to context.rs later
@@ -463,10 +477,6 @@ mod tests { https://github.com/ruby/ruby/blob/trunk/yjit/src/ir.rs#L477
         asm.mov(loc0, dup_val);
     }
 
-
-
-
-    // TODO
     fn guard_object_is_heap(
         asm: &mut Assembler,
         object_opnd: Opnd,
-- 
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