ruby-changes:68593
From: Alan <ko1@a...>
Date: Thu, 21 Oct 2021 08:10:20 +0900 (JST)
Subject: [ruby-changes:68593] 7fbf6d4019 (master): Move registers into header and make them static
https://git.ruby-lang.org/ruby.git/commit/?id=7fbf6d4019 From 7fbf6d4019cfb738095e06c3b017725a0eb1baf0 Mon Sep 17 00:00:00 2001 From: Alan Wu <XrXr@u...> Date: Sat, 3 Oct 2020 18:35:15 -0400 Subject: Move registers into header and make them static We were leaking these as global symbols and were having linking errors with Clang 12. --- ujit_asm.c | 78 ------------------------------------ ujit_asm.h | 132 ++++++++++++++++++++++++++++++------------------------------- 2 files changed, 66 insertions(+), 144 deletions(-) diff --git a/ujit_asm.c b/ujit_asm.c index d2f0c1484e..468aa4af7f 100644 --- a/ujit_asm.c +++ b/ujit_asm.c @@ -8,84 +8,6 @@ https://github.com/ruby/ruby/blob/trunk/ujit_asm.c#L8 #include "ujit_asm.h" -// Dummy none/null operand -const x86opnd_t NO_OPND = { OPND_NONE, 0, .imm = 0 }; - -// Instruction pointer -const x86opnd_t RIP = { OPND_REG, 64, .reg = { REG_IP, 5 }}; - -// 64-bit GP registers -const x86opnd_t RAX = { OPND_REG, 64, .reg = { REG_GP, 0 }}; -const x86opnd_t RCX = { OPND_REG, 64, .reg = { REG_GP, 1 }}; -const x86opnd_t RDX = { OPND_REG, 64, .reg = { REG_GP, 2 }}; -const x86opnd_t RBX = { OPND_REG, 64, .reg = { REG_GP, 3 }}; -const x86opnd_t RSP = { OPND_REG, 64, .reg = { REG_GP, 4 }}; -const x86opnd_t RBP = { OPND_REG, 64, .reg = { REG_GP, 5 }}; -const x86opnd_t RSI = { OPND_REG, 64, .reg = { REG_GP, 6 }}; -const x86opnd_t RDI = { OPND_REG, 64, .reg = { REG_GP, 7 }}; -const x86opnd_t R8 = { OPND_REG, 64, .reg = { REG_GP, 8 }}; -const x86opnd_t R9 = { OPND_REG, 64, .reg = { REG_GP, 9 }}; -const x86opnd_t R10 = { OPND_REG, 64, .reg = { REG_GP, 10 }}; -const x86opnd_t R11 = { OPND_REG, 64, .reg = { REG_GP, 11 }}; -const x86opnd_t R12 = { OPND_REG, 64, .reg = { REG_GP, 12 }}; -const x86opnd_t R13 = { OPND_REG, 64, .reg = { REG_GP, 13 }}; -const x86opnd_t R14 = { OPND_REG, 64, .reg = { REG_GP, 14 }}; -const x86opnd_t R15 = { OPND_REG, 64, .reg = { REG_GP, 15 }}; - -// 32-bit GP registers -const x86opnd_t EAX = { OPND_REG, 32, .reg = { REG_GP, 0 }}; -const x86opnd_t ECX = { OPND_REG, 32, .reg = { REG_GP, 1 }}; -const x86opnd_t EDX = { OPND_REG, 32, .reg = { REG_GP, 2 }}; -const x86opnd_t EBX = { OPND_REG, 32, .reg = { REG_GP, 3 }}; -const x86opnd_t ESP = { OPND_REG, 32, .reg = { REG_GP, 4 }}; -const x86opnd_t EBP = { OPND_REG, 32, .reg = { REG_GP, 5 }}; -const x86opnd_t ESI = { OPND_REG, 32, .reg = { REG_GP, 6 }}; -const x86opnd_t EDI = { OPND_REG, 32, .reg = { REG_GP, 7 }}; -const x86opnd_t R8D = { OPND_REG, 32, .reg = { REG_GP, 8 }}; -const x86opnd_t R9D = { OPND_REG, 32, .reg = { REG_GP, 9 }}; -const x86opnd_t R10D = { OPND_REG, 32, .reg = { REG_GP, 10 }}; -const x86opnd_t R11D = { OPND_REG, 32, .reg = { REG_GP, 11 }}; -const x86opnd_t R12D = { OPND_REG, 32, .reg = { REG_GP, 12 }}; -const x86opnd_t R13D = { OPND_REG, 32, .reg = { REG_GP, 13 }}; -const x86opnd_t R14D = { OPND_REG, 32, .reg = { REG_GP, 14 }}; -const x86opnd_t R15D = { OPND_REG, 32, .reg = { REG_GP, 15 }}; - -// 16-bit GP registers -const x86opnd_t AX = { OPND_REG, 16, .reg = { REG_GP, 0 }}; -const x86opnd_t CX = { OPND_REG, 16, .reg = { REG_GP, 1 }}; -const x86opnd_t DX = { OPND_REG, 16, .reg = { REG_GP, 2 }}; -const x86opnd_t BX = { OPND_REG, 16, .reg = { REG_GP, 3 }}; -const x86opnd_t SP = { OPND_REG, 16, .reg = { REG_GP, 4 }}; -const x86opnd_t BP = { OPND_REG, 16, .reg = { REG_GP, 5 }}; -const x86opnd_t SI = { OPND_REG, 16, .reg = { REG_GP, 6 }}; -const x86opnd_t DI = { OPND_REG, 16, .reg = { REG_GP, 7 }}; -const x86opnd_t R8W = { OPND_REG, 16, .reg = { REG_GP, 8 }}; -const x86opnd_t R9W = { OPND_REG, 16, .reg = { REG_GP, 9 }}; -const x86opnd_t R10W = { OPND_REG, 16, .reg = { REG_GP, 10 }}; -const x86opnd_t R11W = { OPND_REG, 16, .reg = { REG_GP, 11 }}; -const x86opnd_t R12W = { OPND_REG, 16, .reg = { REG_GP, 12 }}; -const x86opnd_t R13W = { OPND_REG, 16, .reg = { REG_GP, 13 }}; -const x86opnd_t R14W = { OPND_REG, 16, .reg = { REG_GP, 14 }}; -const x86opnd_t R15W = { OPND_REG, 16, .reg = { REG_GP, 15 }}; - -// 8-bit GP registers -const x86opnd_t AL = { OPND_REG, 8, .reg = { REG_GP, 0 }}; -const x86opnd_t CL = { OPND_REG, 8, .reg = { REG_GP, 1 }}; -const x86opnd_t DL = { OPND_REG, 8, .reg = { REG_GP, 2 }}; -const x86opnd_t BL = { OPND_REG, 8, .reg = { REG_GP, 3 }}; -const x86opnd_t SPL = { OPND_REG, 8, .reg = { REG_GP, 4 }}; -const x86opnd_t BPL = { OPND_REG, 8, .reg = { REG_GP, 5 }}; -const x86opnd_t SIL = { OPND_REG, 8, .reg = { REG_GP, 6 }}; -const x86opnd_t DIL = { OPND_REG, 8, .reg = { REG_GP, 7 }}; -const x86opnd_t R8B = { OPND_REG, 8, .reg = { REG_GP, 8 }}; -const x86opnd_t R9B = { OPND_REG, 8, .reg = { REG_GP, 9 }}; -const x86opnd_t R10B = { OPND_REG, 8, .reg = { REG_GP, 10 }}; -const x86opnd_t R11B = { OPND_REG, 8, .reg = { REG_GP, 11 }}; -const x86opnd_t R12B = { OPND_REG, 8, .reg = { REG_GP, 12 }}; -const x86opnd_t R13B = { OPND_REG, 8, .reg = { REG_GP, 13 }}; -const x86opnd_t R14B = { OPND_REG, 8, .reg = { REG_GP, 14 }}; -const x86opnd_t R15B = { OPND_REG, 8, .reg = { REG_GP, 15 }}; - // Compute the number of bits needed to encode a signed value size_t sig_imm_size(int64_t imm) { diff --git a/ujit_asm.h b/ujit_asm.h index a52a9691df..07295b23a9 100644 --- a/ujit_asm.h +++ b/ujit_asm.h @@ -132,82 +132,82 @@ typedef struct X86Opnd https://github.com/ruby/ruby/blob/trunk/ujit_asm.h#L132 } x86opnd_t; // Dummy none/null operand -const x86opnd_t NO_OPND; +static const x86opnd_t NO_OPND = { OPND_NONE, 0, .imm = 0 }; // Instruction pointer -const x86opnd_t RIP; +static const x86opnd_t RIP = { OPND_REG, 64, .reg = { REG_IP, 5 }}; // 64-bit GP registers -const x86opnd_t RAX; -const x86opnd_t RCX; -const x86opnd_t RDX; -const x86opnd_t RBX; -const x86opnd_t RBP; -const x86opnd_t RSP; -const x86opnd_t RSI; -const x86opnd_t RDI; -const x86opnd_t R8; -const x86opnd_t R9; -const x86opnd_t R10; -const x86opnd_t R11; -const x86opnd_t R12; -const x86opnd_t R13; -const x86opnd_t R14; -const x86opnd_t R15; +static const x86opnd_t RAX = { OPND_REG, 64, .reg = { REG_GP, 0 }}; +static const x86opnd_t RCX = { OPND_REG, 64, .reg = { REG_GP, 1 }}; +static const x86opnd_t RDX = { OPND_REG, 64, .reg = { REG_GP, 2 }}; +static const x86opnd_t RBX = { OPND_REG, 64, .reg = { REG_GP, 3 }}; +static const x86opnd_t RSP = { OPND_REG, 64, .reg = { REG_GP, 4 }}; +static const x86opnd_t RBP = { OPND_REG, 64, .reg = { REG_GP, 5 }}; +static const x86opnd_t RSI = { OPND_REG, 64, .reg = { REG_GP, 6 }}; +static const x86opnd_t RDI = { OPND_REG, 64, .reg = { REG_GP, 7 }}; +static const x86opnd_t R8 = { OPND_REG, 64, .reg = { REG_GP, 8 }}; +static const x86opnd_t R9 = { OPND_REG, 64, .reg = { REG_GP, 9 }}; +static const x86opnd_t R10 = { OPND_REG, 64, .reg = { REG_GP, 10 }}; +static const x86opnd_t R11 = { OPND_REG, 64, .reg = { REG_GP, 11 }}; +static const x86opnd_t R12 = { OPND_REG, 64, .reg = { REG_GP, 12 }}; +static const x86opnd_t R13 = { OPND_REG, 64, .reg = { REG_GP, 13 }}; +static const x86opnd_t R14 = { OPND_REG, 64, .reg = { REG_GP, 14 }}; +static const x86opnd_t R15 = { OPND_REG, 64, .reg = { REG_GP, 15 }}; // 32-bit GP registers -const x86opnd_t EAX; -const x86opnd_t ECX; -const x86opnd_t EDX; -const x86opnd_t EBX; -const x86opnd_t EBP; -const x86opnd_t ESP; -const x86opnd_t ESI; -const x86opnd_t EDI; -const x86opnd_t R8D; -const x86opnd_t R9D; -const x86opnd_t R10D; -const x86opnd_t R11D; -const x86opnd_t R12D; -const x86opnd_t R13D; -const x86opnd_t R14D; -const x86opnd_t R15D; +static const x86opnd_t EAX = { OPND_REG, 32, .reg = { REG_GP, 0 }}; +static const x86opnd_t ECX = { OPND_REG, 32, .reg = { REG_GP, 1 }}; +static const x86opnd_t EDX = { OPND_REG, 32, .reg = { REG_GP, 2 }}; +static const x86opnd_t EBX = { OPND_REG, 32, .reg = { REG_GP, 3 }}; +static const x86opnd_t ESP = { OPND_REG, 32, .reg = { REG_GP, 4 }}; +static const x86opnd_t EBP = { OPND_REG, 32, .reg = { REG_GP, 5 }}; +static const x86opnd_t ESI = { OPND_REG, 32, .reg = { REG_GP, 6 }}; +static const x86opnd_t EDI = { OPND_REG, 32, .reg = { REG_GP, 7 }}; +static const x86opnd_t R8D = { OPND_REG, 32, .reg = { REG_GP, 8 }}; +static const x86opnd_t R9D = { OPND_REG, 32, .reg = { REG_GP, 9 }}; +static const x86opnd_t R10D = { OPND_REG, 32, .reg = { REG_GP, 10 }}; +static const x86opnd_t R11D = { OPND_REG, 32, .reg = { REG_GP, 11 }}; +static const x86opnd_t R12D = { OPND_REG, 32, .reg = { REG_GP, 12 }}; +static const x86opnd_t R13D = { OPND_REG, 32, .reg = { REG_GP, 13 }}; +static const x86opnd_t R14D = { OPND_REG, 32, .reg = { REG_GP, 14 }}; +static const x86opnd_t R15D = { OPND_REG, 32, .reg = { REG_GP, 15 }}; // 16-bit GP registers -const x86opnd_t AX; -const x86opnd_t CX; -const x86opnd_t DX; -const x86opnd_t BX; -const x86opnd_t SP; -const x86opnd_t BP; -const x86opnd_t SI; -const x86opnd_t DI; -const x86opnd_t R8W; -const x86opnd_t R9W; -const x86opnd_t R10W; -const x86opnd_t R11W; -const x86opnd_t R12W; -const x86opnd_t R13W; -const x86opnd_t R14W; -const x86opnd_t R15W; +static const x86opnd_t AX = { OPND_REG, 16, .reg = { REG_GP, 0 }}; +static const x86opnd_t CX = { OPND_REG, 16, .reg = { REG_GP, 1 }}; +static const x86opnd_t DX = { OPND_REG, 16, .reg = { REG_GP, 2 }}; +static const x86opnd_t BX = { OPND_REG, 16, .reg = { REG_GP, 3 }}; +static const x86opnd_t SP = { OPND_REG, 16, .reg = { REG_GP, 4 }}; +static const x86opnd_t BP = { OPND_REG, 16, .reg = { REG_GP, 5 }}; +static const x86opnd_t SI = { OPND_REG, 16, .reg = { REG_GP, 6 }}; +static const x86opnd_t DI = { OPND_REG, 16, .reg = { REG_GP, 7 }}; +static const x86opnd_t R8W = { OPND_REG, 16, .reg = { REG_GP, 8 }}; +static const x86opnd_t R9W = { OPND_REG, 16, .reg = { REG_GP, 9 }}; +static const x86opnd_t R10W = { OPND_REG, 16, .reg = { REG_GP, 10 }}; +static const x86opnd_t R11W = { OPND_REG, 16, .reg = { REG_GP, 11 }}; +static const x86opnd_t R12W = { OPND_REG, 16, .reg = { REG_GP, 12 }}; +static const x86opnd_t R13W = { OPND_REG, 16, .reg = { REG_GP, 13 }}; +static const x86opnd_t R14W = { OPND_REG, 16, .reg = { REG_GP, 14 }}; +static const x86opn (... truncated) -- ML: ruby-changes@q... Info: http://www.atdot.net/~ko1/quickml/